View AT17C002_1027585.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Features
* EE Reprogrammable 2,097,152 x 1-bit Serial Memories Designed to Store
Configuration Programs for Field Programmable Gate Arrays (FPGAs)
* In-System Programmable via 2-wire Bus * Simple Interface to SRAM FPGAs * Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX(R), APEXTM * * * * * * * * *
Devices, Lucent ORCA(R) FPGAs, Xilinx XC3000TM, XC4000TM, XC5200TM, Spartan(R), VirtexTM FPGAs Cascadable Read Back to Support Additional Configurators or Higher-density Arrays Low-power CMOS EEPROM Process Programmable Reset Polarity Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC Packages), 20-lead PLCC, 44-lead PLCC and 44-lead TQFP Packages (Pin-compatible Across Product Family) Emulation of Atmel's AT24CXXX Serial EEPROMs Available in 3.3V 10% LV and 5V 5% C Versions System-friendly READY Pin Low-power Standby Mode Replacement for AT17C/LV020
FPGA Configuration EEPROM Memory
2-megabit
Description
The AT17C002 and AT17LV002 (high-density AT17 Series) FPGA Configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for programming Field Programmable Gate Arrays. The AT17 Series is packaged in the popular 8-lead LAP, 20-lead PLCC, 44-lead PLCC and the 44-lead TQFP. The AT17 Series family uses a simple serial-access procedure to configure one or more FPGA devices. The user can select the polarity of the reset function by programming four EEPROM bytes. These devices support a write protection mode and a systemfriendly READY pin, which signifies a "good" power level to the FPGA and can be used to ensure reliable system power-up. The AT17 Series Configurators can be programmed with industry-standard programmers, Atmel's ATDH2200E Programming System and Atmel's ATDH2225 ISP Cable.
AT17C002 AT17LV002
Rev. 2281D-12/01
1
Pin Configuration
8-lead LAP 20-lead PLCC
DATA CLK RESET/OE CE
1 2 3 4
8 7 6 5
VCC SER_EN CEO (A2) GND
3 2 1 20 19
44-lead TQFP
NC DATA NC VCC NC
44 43 42 41 40 39 38 37 36 35 34 NC CLK NC NC DATA NC VCC NC NC SER_EN NC
44-lead PLCC
NC CLK NC NC DATA NC VCC NC NC SER_EN NC
6 5 4 3 2 1 44 43 42 41 40
18 19 20 21 22 23 24 25 26 27 28
2
AT17C/LV002
2281D-12/01
NC RESET/OE NC CE NC NC GND NC NC CEO(A2) NC
NC RESET/OE NC CE NC NC GND NC NC CEO(A2) NC
12 13 14 15 16 17 18 19 20 21 22
WP1 NC NC NC NC NC NC NC NC NC NC
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36 35 34 33 32 31 30 29
NC NC NC NC NC NC NC NC NC NC READY
NC GND NC NC NC
9 10 11 12 13
CLK WP1 RESET/OE NC CE
4 5 6 7 8
18 17 16 15 14
NC SER_EN NC READY CEO(A2)
NC NC NC NC NC NC WP1 NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11
33 32 31 30 29 28 27 26 25 24 23
NC NC NC NC NC NC NC NC NC NC READY
AT17C/LV002
Block Diagram
SER_EN WP1 PROGRAMMING DATA SHIFT REGISTER
PROGRAMMING MODE LOGIC
OSC CONTROL ROW ADDRESS COUNTER ROW DECODER OSC
EEPROM CELL MATRIX
POWER ON RESET
BIT COUNTER TC
COLUMN DECODER
CLK READY
RESET/OE
CE
CEO(A2)
DATA
Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration EEPROM without requiring an external intelligent controller. The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven High, the configuration EEPROM resets its address counter and tri-states its DATA pin. The CE pin also controls the output of the AT17 Series Configurator. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven Low, the counter and the DATA output pin are enabled. When RESET/OE is driven High again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE. When the configurator has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset. This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High, this document will describe RESET/OE. 3
2281D-12/01
Pin Configurations
8 LAP Pin 1 2 - 20 PLCC Pin 2 4 5 44 TQFP Pin 40 43 7 44 PLCC Pin 2 5 7 Name DATA CLK WP1(1) I/O I/O I I Description Three-state DATA output for configuration. Open-collector bi-directional pin for programming. Clock input. Used to increment the internal address and bit counter for reading and programming. WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled by default due to internal pull-down resistor. This input pin is not used during FPGA loading operations. Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the data output driver. The logic polarity of this input is programmable as either RESET/OE or RESET/OE. For most applications, RESET should be programmed active Low. This document describes the pin as RESET/OE. Chip Enable input (active Low). A Low level (with OE High) allows DCLK to increment the address counter and enables the data output driver. A High level on CE disables both the address and bit counters and forces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the 2-wire Serial Programming mode (SER_EN Low). Ground pin. A 0.2 F decoupling capacitor between VCC and GND is recommended. O Chip Enable Output (active Low). This output goes Low when the address counter has reached its maximum value. In a daisy chain of AT17 Series devices, the CEO pin of one device must be connected to the CE input of the next device in the chain. It will stay Low as long as CE is low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay High until the entire EEPROM is read again. Device selection input, A2. This is used to enable (or select) the device during programming (i.e., when SER_EN is Low). A2 has an internal pulldown resistor. Open collector reset state indicator. Driven Low during power-up reset, released when power-up is complete. (Recommend a 4.7 k pull-up on this pin if used). Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low enables the 2-wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to VCC. +3.3V/+5V power supply pin.
3
6
13
19
RESET/OE
I
4
8
15
21
CE
I
5
10
18
24
GND CEO
6
14
21
27 A2 I
-
15
23
29
READY(1)
O
7
17
35
41
SER_EN
I
8 Note:
20
38
44
VCC
1. This pin is not available on the 8-lead packages.
4
AT17C/LV002
2281D-12/01
AT17C/LV002
FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA mode pins. In Master Mode, the FPGA automatically loads the configuration program from an external memory. The AT17 Serial Configuration EEPROM has been designed for compatibility with the Master Serial Mode. This document discusses the AT40K, AT40KAL and AT94KAL applications, as well as Xilinx applications.
Control of Configuration
Most connections between the FPGA device and the AT17 Serial EEPROM are simple and self-explanatory: * * * * * The DATA output of the AT17 Series Configurator drives DIN of the FPGA devices. The master FPGA CCLK output drives the CLK input of the AT17 Series Configurator. The CEO output of any AT17 Series Configurator drives the CE input of the next Configurator in a cascade chain of EEPROMs. SER_EN must be connected to VCC (except during ISP). The READY pin is available as an open-collector indicator of the device's reset status; it is driven Low while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete.
Cascading Serial Configuration EEPROMs
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories, cascaded Configurators provide additional memory. As the last bit from the first Configurator is read, the clock signal to the Configurator asserts its CEO output Low and disables its DATA line driver. The second Configurator recognizes the Low level on its CE input and enables its DATA output. After configuration is complete, the address counters of all cascaded Configurators are reset if the RESET/OE on each Configurator is driven to its active (Low) level. If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to its inactive (High) level.
AT17 Series Reset Polarity Programming Mode
The AT17 Series Configurator allows the user to program the reset polarity as either RESET/OE or RESET/OE. This feature is supported by industry-standard programmer algorithms. The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the 2-wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated inside the chip. The AT17C parts are read/write at 5V nominal. The AT17LV parts are read/write at 3.3V nominal. The AT17C/LV002 Series Configurator enters a low-power standby mode whenever CE is asserted High. In this mode, the Configurator consumes less than 0.5 mA of current at 5V. The output remains in a high-impedance state regardless of the state of the OE input.
Standby Mode
5
2281D-12/01
Example Circuits
Figure 1. AT17 Series Device for Programming PSLI Devices
AT40K/AT40KAL/AT94K RESET RESET DATA0 CCLK CON INIT
AT17 Series Device SER_EN DATA CLK CE (2) RESET/OE(1) READY
VCC
M2 M1 M0
GND
Notes:
1. Reset polarity must be set to active Low. 2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
The FPGA CON/DONE output drives the CE input of the AT17 Series Configurator, while the RESET/OE input is driven by the FPGA INIT pin. This connection works under all normal circumstances, even when the user aborts the configuration before CON/DONE has gone High. A Low level on the RESET/OE input, during FPGA reset, clears the configurator's internal address pointer so that the reconfiguration starts at the beginning. Figure 2. Drop-In Replacement of XC17/ATT17 PROMs for Xilinx/Lucent FPGA Applications
VCC
4.7 k9
XILINX FPGA PROGRAM PROGRAM DIN CCLK DONE(3) INIT
AT17 Series Device SER_EN DATA CLK CE (2) RESET/OE(1) READY
VCC
M2 M1 M0
GND
Notes:
1. Reset polarity must be set to active Low. 2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices. 3. An internal pull-up resistor is enabled here for DONE.
6
AT17C/LV002
2281D-12/01
AT17C/LV002
For details of ISP, please refer to the "Programming Specification for Atmel's AT17 and AT17A Series FPGA Configuration EEPROMs", available on the Atmel web site, at http://www.atmel.com/atmel/acrobat/doc0437.pdf. Figure 3. In-System Programming of AT17 Series for PSLI Applications
VCC VCC
4.7 k9 4.7 k9
DATA 1 SCLK 3
5 7 9
2 4 6 8 10
VCC
GND
AT40K/AT40KAL/AT94K RESET RESET DATA0 CCLK CON INIT
AT17 Series Device SER_EN DATA CLK CE (2) RESET/OE(1) READY SER_EN
M2 M1 M0
GND
Notes:
1. Reset polarity must be set to active Low. 2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
Figure 4. In-System Programming of AT17 Series for Xilinx/Lucent FPGA Applications
VCC VCC
4.7 k9 4.7 k9
DATA 1 SCLK 3
5
2 4 6 8 10
VCC
VCC
4.7 k9
VCC
4.7 k9
7 9
XILINX FPGA PROGRAM PROGRAM DIN CCLK DONE(3) INIT
AT17 Series Device SER_EN DATA CLK CE (1) READY(2) RESET/OE
GND
SER_EN
M2 M1 M0
GND
Notes:
1. Reset polarity must be set to active Low. 2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices. 3. An internal pull-up resistor is enabled here for DONE.
7
2281D-12/01
Absolute Maximum Ratings*
Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65 C to +150C Voltage on Any Pin with Respect to Ground ..............................-0.1V to VCC +0.5V Supply Voltage (VCC) .........................................-0.5V to +7.0V Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260C ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.
Operating Conditions
AT17C002 Symbol Description Commercial Industrial Military Supply voltage relative to GND, -0C to +70C Supply voltage relative to GND, -40C to +85C Supply voltage relative to GND, -55C to +125C Min 4.75 4.5 Max 5.25 5.5 AT17LV002 Min 3.0 3.0 Max 3.6 3.6 Units V V
VCC
4.5
5.5
3.0
3.6
V
8
AT17C/LV002
2281D-12/01
AT17C/LV002
DC Characteristics
VCC = 5V 5% Commercial, 5V 10% Industrial/Military
Symbol VIH VIL VOH VOL VOH VOL VOH VOL ICCA IL ICCS1 ICCS2 Description High-Level Input Voltage Low-level input voltage High-level Output Voltage (IOH = -4 mA) Low-level Output Voltage (IOL = +4 mA) High-level Output Voltage (IOH = -4 mA) Low-level Output Voltage (IOL = +4 mA) High-level Output Voltage (IOH = -4 mA) Low-level Output Voltage (IOL = +4 mA) Supply Current, Active Mode Input or Output Leakage Current (VIN = VCC or GND) Commercial Supply Current, Standby Mode, CMOS Industrial/Military Supply Current, Standby Mode, TTL Commercial/Industrial 0.75 1 mA mA -10 3.7 Military 0.4 10 10 0.5 V mA A mA 3.76 Industrial 0.37 V V Commercial 0.32 V V Min 2.0 0.0 3.86 Max VCC 0.8 Units V V V
DC Characteristics
VCC = 3.3V 10%
Symbol VIH VIL VOH VOL VOH VOL VOH VOL ICCA IL ICCS Description High-level input voltage Low-level input voltage High-level Output Voltage (IOH = -2.5 mA) Low-level Output Voltage (IOL = +3 mA) High-level Output Voltage (IOH = -2 mA) Low-level Output Voltage (IOL = +3 mA) High-level Output Voltage (IOH = -2 mA) Low-level Output Voltage (IOL = +2.5 mA) Supply Current, Active Mode Input or Output Leakage Current (VIN = VCC or GND) Commercial Supply Current, Standby Mode Industrial/Military 200 A -10 2.4 Military 0.4 5 10 200 V mA A A 2.4 Industrial 0.4 V V Commercial 0.4 V V Min 2.0 0.0 2.4 Max VCC 0.8 Units V V V
9
2281D-12/01
AC Characteristics
CE TSCE RESET/OE TLC CLK TOE TCE DATA TOH TCAC TOH TDF THC THOE TSCE THCE
AC Characteristics when Cascading
RESET/OE
CE
CLK TCDF DATA
LAST BIT FIRST BIT
TOCK CEO
TOCE
TOOE
TOCE
10
AT17C/LV002
2281D-12/01
AT17C/LV002
.
AC Characteristics for AT17C002
VCC = 5V 5% Commercial, VCC = 5V 10% Industrial/Military
Commercial Symbol TOE(2) TCE
(2) (2)
Industrial/Military(1) Min Max 35 45 50 0 Units ns ns ns ns 50 20 20 25 0 20 15 ns ns ns ns ns ns MHz
Description OE to Data Delay CE to Data Delay CLK to Data Delay Data Hold From CE, OE or CLK CE or OE to Data Float Delay CLK Low Time CLK High Time CE Setup Time to CLK (to guarantee proper counting) CE Hold Time from CLK (to guarantee proper counting) OE High Time (guarantees counter is reset) Maximum Input Clock Frequency
Min
Max 30 45 50
TCAC TOH
0 50 20 20 20 0 20 15
TDF(3) TLC THC TSCE THCE THOE FMAX Notes:
1. Preliminary specifications for military operating range only. 2. AC test load = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels.
AC Characteristics for AT17C002 when Cascading
VCC = 5V 5% Commercial/VCC = 5V 10% Industrial/Military
Commercial Symbol TCDF (3) TOCK(2) TOCE(2) TOOE(2) FMAX Notes: Description CLK to Data Float Delay CLK to CEO Delay CE to CEO Delay RESET/OE to CEO Delay Maximum Input Clock Frequency 12.5 Min Max 50 35 35 30 12.5 Industrial/Military(1) Min Max 50 40 35 30 Units ns ns ns ns MHz
1. Preliminary specifications for military operating range only. 2. AC test load = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels.
11
2281D-12/01
AC Characteristics for AT17LV002
VCC = 3.3V 10%
Commercial Symbol TOE(2) TCE
(2) (2)
Industrial/Military(1) Min Max 55 60 60 0 Units ns ns ns ns 50 25 25 35 0 25 10 ns ns ns ns ns ns MHz
Description OE to Data Delay CE to Data Delay CLK to Data Delay Data Hold From CE, OE or CLK CE or OE to Data Float Delay CLK Low Time CLK High Time CE Setup Time to CLK (to guarantee proper counting) CE Hold Time from CLK (to guarantee proper counting) OE High Time (guarantees counter is reset) Maximum Input Clock Frequency
Min
Max 50 55 55
TCAC TOH
0 50 25 25 30 0 25 15
TDF(3) TLC THC TSCE THCE THOE FMAX Notes:
1. Preliminary specifications for military operating range only. 2. AC test load = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels.
AC Characteristics for AT17LV002 when Cascading
VCC = 3.3V 10%
Commercial Symbol TCDF(3) TOCK(2) TOCE(2) TOOE(2) FMAX Notes: Description CLK to Data Float Delay CLK to CEO Delay CE to CEO Delay RESET/OE to CEO Delay Maximum Input Clock Frequency 12.5 Min Max 50 50 35 35 10 Industrial/Military(1) Min Max 50 55 40 35 Units ns ns ns ns MHz
1. Preliminary specifications for military operating range only. 2. AC test load = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels.
12
AT17C/LV002
2281D-12/01
AT17C/LV002
Thermal Resistance Coefficients(1)
Package Type Leadless Array Package (LAP) Plastic Leaded Chip Carrier (PLCC) Thin Plastic Quad Flat Package (TQFP) Plastic Leaded Chip Carrier (PLCC) Note: 8CN4 20J 44A 44J JC [C/W] 45 35 17 15 JA [C/W] Airflow = 0 ft/min 159.60 90 62 50
1. For more information refer to the "Thermal Characteristics of Atmel's Packages", available on the Atmel web site, at http://www.atmel.com/atmel/acrobat/doc0636.pdf.
13
2281D-12/01
Ordering Information - 5V Devices
Memory Size 2-Mbit Ordering Code AT17C002-10CC AT17C002-10JC AT17C002-10TQC AT17C002-10BJC AT17C002-10CI AT17C002-10JI AT17C002-10TQI AT17C002-10BJI Package 8CN4 20J 44A 44J 8CN4 20J 44A 44J Operation Range Commercial (0C to 70C)
Industrial (-40C to 85C)
Ordering Information - 3.3V Devices
Memory Size 2-Mbit Ordering Code AT17LV002-10CC AT17LV002-10JC AT17LV002-10TQC AT17LV002-10BJC AT17LV002-10CI AT17LV002-10JI AT17LV002-10TQI AT17LV002-10BJI Package 8CN4 20J 44A 44J 8CN4 20J 44A 44J Operation Range Commercial (0C to 70C)
Industrial (-40C to 85C)
Package Type 8CN4 20J 44A 44J 8-lead, 6 mm x 6 mm x 1 mm, Leadless Array Package (LAP) - Pin-compatible with 8-lead SOIC/VOIC Packages 20-lead, Plastic J-leaded Chip Carrier (PLCC) 44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP) 44-lead, Plastic J-leaded Chip Carrier (PLCC)
14
AT17C/LV002
2281D-12/01
AT17C/LV002
Packaging Information
8CN4 - LAP
Marked Pin1 Indentifier
E
D
A A1
Top View
0.10 mm TYP
Side View
L1
Pin1 Corner
8
1
e
7 2
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 0.94 0.30 0.45 5.89 4.89 NOM 1.04 0.34 0.50 5.99 5.99 1.27 BSC 1.10 REF 0.95 1.25 1.00 1.30 1.05 1.35 1 1 MAX 1.14 0.38 0.55 6.09 6.09 1 NOTE
6
3
A
b
5 4
A1 b D E
e1
L
e e1 L L1
Bottom View
Note: 1. Metal Pad Dimensions.
11/14/01 1150 E.Cheyenne Mtn Blvd. Colorado Springs, CO 80906 TITLE 8CN4, 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm, Leadless Array Package (LAP) DRAWING NO. 8CN4 REV. A
R
15
2281D-12/01
20J - PLCC
1.14(0.045) X 45
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45
0.318(0.0125) 0.191(0.0075)
e E1 B E B1 D2/E2
D1 D A
A2 A1
0.51(0.020)MAX 45 MAX (3X)
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 9.779 8.890 9.779 8.890 7.366 0.660 0.330 NOM - - - - - - - - - - 1.270 TYP MAX 4.572 3.048 - 10.033 9.042 10.033 9.042 8.382 0.813 0.533 Note 2 Note 2 NOTE
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 20J REV. B
R
16
AT17C/LV002
2281D-12/01
AT17C/LV002
44A - TQFP
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 11.75 9.90 11.75 9.90 0.30 0.09 0.45 NOM - - 1.00 12.00 10.00 12.00 10.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 12.25 10.10 12.25 10.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 44A REV. B
R
17
2281D-12/01
44J - PLCC
1.14(0.045) X 45 PIN NO. 1 IDENTIFIER 1.14(0.045) X 45 0.318(0.0125) 0.191(0.0075)
E1 B
E
B1
D2/E2
e D1 D A A2 A1
0.51(0.020)MAX 45 MAX (3X)
SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e
COMMON DIMENSIONS (Unit of Measure = mm) MIN 4.191 2.286 0.508 17.399 16.510 17.399 16.510 14.986 0.660 0.330 NOM - - - - - - - - - - 1.270 TYP MAX 4.572 3.048 - 17.653 16.662 17.653 16.662 16.002 0.813 0.533 Note 2 Note 2 NOTE
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 44J REV. B
R
18
AT17C/LV002
2281D-12/01
Atmel Headquarters
Corporate Headquarters
2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600
Atmel Operations
Memory
Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314
RF/Automotive
Atmel Heilbronn Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759
Europe
Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500
Microcontrollers
Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314 Atmel Nantes La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60
Asia
Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80
ASIC/ASSP/Smart Cards
Atmel Rousset Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Atmel Smart Card ICs Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743
Japan
Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581
Atmel Configurator Hotline
(408) 436-4119
e-mail
literature@atmel.com
Atmel Configurator e-mail
configurator@atmel.com
Web Site
http://www.atmel.com
FAQ
Available on web site
(c) Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Atmel(R) is the registered trademark of Atmel. FLEX (R) is the registered trademark of Altera Corporation; ORCA (R) is the registered of Lucent Technologies, Inc.; Spartan(R) is the registered trademark of Xilinx, Inc. XC3000TM, XC4000TM, XC5200TM and Virtex TM are the trademarks of Xilinx, Inc. Other terms and product names may be trademarks of others. Printed on recycled paper.
2281D-12/01/xM

▲Up To Search▲

Price & Availability of AT17C002

	To Download AT17C002 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .